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3.2
AT91SAM9G10 Block Diagram
Figure 3-1.
Block Diagram
MMU
Interface
JTAGSEL
TDI
TDO
TMS
TCK
NTRST
RTCK
JTAG
Boundary Scan
System Controller
ICE
ARM926EJ-S Core
Instruction Cache Data Cache
16K bytes 16K bytes
TCM
BIU
ETM
TSYNC
TCLK
TPS0-TPS2
TPK0-TPK15
BMS
TST
FIQ
IRQ0-IRQ2
DRXD
DTXD
PCK0-PCK3
PLLRCA
PLLRCB
XIN
XOUT
XIN32
XOUT32
AIC
DBGU
PDC
PLLA
PMC
PLLB
OSC
WDT
PIT
GPBREG
OSC RTT
I D
ITCM DTCM
Fast SRAM
160K bytes
Fast ROM
32K bytes
Peripheral
Bridge
Peripheral
I
5-layer
Matrix
D
EBI
CompactFlash
NAND Flash
SDRAM
Controller
Static
Memory
Controller
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15/A18-A21
A22/REG
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NCS2
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS-CAS
SDWE
SDA10
NWAIT
A23-A24
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
CFCE1
CFCE2
SHDN
WKUP
SHDWC
DMA
Controller
NCS6/NANDOE
NCS7/NANDWE
D16-D31
VDDBU
POR
DMA
FIFO
HDMA
HDPA
GNDBU
RSTC
VDDCORE
NRST
POR
APB
FIFO
USB Host
HDMB
HDPB
PIOA
PIOB
PIOC
USB Device
DDM
DDP
DMA
LCDD0-LCDD23
MCCK
MCCDA
MCDA0-MCDA3
MCI
PDC
FIFO
LUT
LCD Controller
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDCC
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
USART1
PDC
PDC
PDC
SSC0
SSC1
TF0
TK0
TD0
RD0
RK0
RF0
TF1
TK1
TD1
RD1
RK1
RXD2
TXD2
SCK2
RTS2
USART2
PDC
RF1
TF2
TK2
TD2
CTS2
SPI0_NPCS0
PDC
PDC
SSC2
RD2
RK2
RF2
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI1_NPCS10
SPI1_NPCS1
SPI1_NPCS12
SPI0
PDC
Timer Counter
TC0
TC1
TC2
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1
PDC
TWI
TWD
TWCK
3-4
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
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